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CADSTAR FPGA
(UPDATED May 21, 2008)

Request the CADSTAR FPGA Software, 30 day evaluation license (MAC address is required) and Self Teach tutorial

To receive CADSTAR FPGA please submit your details in the form below, accept the Zuken Privacy Policy and select the 'Submit' button.
An email will be sent to your email address you supplied previously (listed below) containing links to download the software.

After you have received the evaluation license the software expires after 30 days. You will download herewith the CADSTAR FPGA software as currently available.

Please be aware that CADSTAR FPGA has some functionality limitations compared to the full commercial release of Aldec. Please review below the list of limitations:

  • Simulation Performance Limitations compared to full commercial release:
    • Simulation run time is limited to 2 ms
    • Performance limitation 6x slowdown (up to 2,000 design instances)
    • Performance limitation 20x slowdown (2001 upon 10,000 design instances)
    • Ceiling limitation - above 10,000 instances - simulation runs at 1% of full commercial release
    • Full details of other limitations are available in the FPGA datasheet

Download the CADSTAR FPGA tutorial here:

PDF File 3.5 Mb CADSTAR FPGA Tutorial screen version
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