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CADSTAR Express
FREE
CADSTAR 9.0 PCB Design Software
(Software updated: July 16, 2007)
- CADSTAR Express Datasheet
- CADSTAR Express recommended minimum configurtation
CADSTAR Express provides a quick and easy way for you to experience the basic features of a standard PCB solution. It includes all the functionality of CADSTAR 9.0, limited to 300 pins and 50 components, plus the opportunity to experience Zuken's advanced P.R.Editor XR 2000.
In addition you are also able to view samples of CADSTAR Exchange*, a 200,000 component on-line library.
NOTE: This is not the full library of components but a sample to illustrate the benefits of CADSTAR Exchange. It does not contain the downloadable zip files containing Schematic symbols, PCB footprint and part library information which Exchange users are able to add to their CADSTAR library.
Inconjunction with this latest release of CADSTAR Express we have also improved and updated the 'Do-It-Yourself' manual to guide you through the PCB Design process and help you evaluate the potential of CADSTAR Express.
- (The 'Do-It-Yourself' manual is also available to download separately
- click here)
CADSTAR Express offers a glance into the process of designing a simple PCB.
However, should your needs dictate a more comprehensive evaluation of CADSTAR please contact your local CADSTAR distributor to request a full evaluation version of CADSTAR solutions.
- The following significant functional areas are
NOT AVAILABLE within CADSTAR Express...
CADSTAR FPGA
Preview of CADSTAR FPGA - 30 day evaluation version
(Software updated: February 7, 2008)
- CADSTAR FPGA Datasheet (748 Kb)
- CADSTAR software recommended minimum configuration
- CADSTAR FPGA evaluation limitation details 
3.5 Mb CADSTAR FPGA Tutorial screen version
Register to download the software (30 day free evaluation version), and have sneak preview on CADSTAR FPGA.
CADSTAR FPGA combines Aldec’s Active-HDL Lite design simulation environment and Zuken’s desktop PCB design suite, CADSTAR. Engineers can perform comprehensive FPGA designs with complete support for technology from multiple FPGA vendors including Actel, Altera, Lattice, Quicklogic and Xilinx. It also performs mixed VHDL and Verilog simulation, strictly adhering to the latest IEEE language standards.
CADSTAR FPGA, provides one universal project manager that controls all design files for simulation, synthesis, place and route and pin assignment to the PCB. This integrated solution supports robust I/O synchronization between the FPGA device and the PCB, helping to optimize the routing pattern for high-density devices like BGAs plus the opportunity to experience Zuken's advanced P.R.Editor XR 2000.
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CADSTAR Design Viewer 10.0
(30 April 2008)
The CADSTAR Design Viewer is a free
product that lets you share and access
CADSTAR design data very easily on any
of your preferred Windows platforms. The
design data is accessible to any user,
even the occasional users, with easy viewing
and sharing of schematic and PCB data.
It dramatically improves workgroup dynamics
by increasing project productivity either
in standalone mode or when used in conjunction
in a CADSTAR design environment.
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EMC
Training System
Zuken
has introduced the EMC Training System, an on-line,
interactive training system for high-speed PCB
design engineers. Zuken's EMC Training System
offers:
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Training
on demand at the engineer's desk Computer
based training using web technology Practical
examples delivered interactively Illustrated
design practice and easy to follow guidelines Flexible
content and easy, regular updates Reduced
training costs
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Independance
from location and time constraints
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CADSTAR - Recommended Minimum Configuration:
- Windows 2000/XP/XP 64
- 1 GHz INTEL Pentium Processor (2 GHz recommended)
- 2 Gb hard disc (NTFS format)
- 250Mb disk space required for full CADSTAR installation and libraries
- 512Mb RAM (1 Gb recommended)
- 512Mb virtual memory / paging file
- 1280 x 1024 display, 256 colours
- CD-ROM drive
- 3 button mouse
- Parallel or USB port
- Microsoft Internet Explorer 4.5, or later.
- Adobe Acrobat Reader
CADSTAR FPGA - Please be aware that this evaluation copy has some functionality limitations.
Please review herewith below the list of limitations compared to full commercial release:
- Simulation run time is limited to 2 ms
- Performance limitation 6x slowdown (up to 2,000 design instances)
- Performance limitation 20x slowdown (2001 upon 10,000 design instances)
- Ceiling limitation - above 10,000 instances - simulation runs at 1% of full commercial release
- Full details of other limitations are available in the FPGA datasheet
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