Function |
Description & Benefit |
| General |
| CADSTAR FPGA |
A new integration with the Active-HDL Lite FPGA design environment from Aldec is available as an additional cost option with CADSTAR 10. |
| E3.logic for CADSTAR |
An integration has been developed which supports initial design transfer from E3.logic to CADSTAR, forward and back-annotation of design changes and cross-probing. CADSTAR will also access the E3 database directly to access library part information. |
Version control of Parts and Components in Library, Schematic and PCB design |
Updates to version information can be handled automatically and comparisons between the versions used in the library and current design can be easily be made. Fully detailed reports are also available. You even may easily select to update all ‘out of date’ parts in a design to match the latest available in the library.
|
Parts information stored in the Schematics and PCB design files |
No Library needed when:
- Running Pin & Gate Swap
- Item Property will get information from Design instead of Library (faster and less access needed to library)
- Transferring to P.R.Editor HSpeed and SI Verify (will load part information from the design instead of library)
- Running the post processing
|
| Control |
Rules By Area |
Design Rules by Area are now supported in Design Editor and will allow you to define specific rules per area in a consistent manner with P.R.Editor
|
| Intelligent Buses in Schematics |
You can now restrict the signals connecting to a bus according to the signal name. When a symbol with multiple terminals is moved so that the terminals are superimposed over a bus, a new connection for each terminal can be connected to the bus. A 'Bus Terminal' is added to each new connection at the point where the connection meets the bus. |
| Multiple Net Highlight Colours |
Highlight colours can now be defined per-net. Net highlighting can be toggled via the right mouse button menu.
Teardrops and test lands are now also highlighted in PCB |
| Parts Library in Design Editor |
Part information is now stored in the Schematics and PCB design files. Create a Parts Library from the design. |
| ODB++ |
Numerous enhancements have been made to the ODB++ output, like: All component copper is written out: export of Component outlines on resist layers: |
| Ease of Use |
Improved GUI |
The new dialog includes the Layer Stack View, a diagram showing a sample cross-section of the stack. Conducting and construction layers are shown and any errors are indicated by colour. Also the old Layers Dialog has now been replaced by one based on a grid. This means you can view the entire layer stack at once. |
| Connection Colours |
You can now show different nets with different colours in Design Editor (Colour By Net). |
| Custom Colours |
The old CADSTAR custom colour dialog has been replaced with the standard Windows dialog. |
| User-defined Attributes for Components and Symbols |
CADSTAR now supports user-defined Attributes for Components and Symbols. |
| Automatic Parts Index Creation |
If the parts library becomes out of date, the user is asked if they want to update it. |
| Improved Design Rule Check |
When the spacing value is set to ‘0’ (zero), overlapping centre lines of placement outlines will no longer create a Component Placement to Component Placement error. |
| PDF Output from Batch Processor |
Previously when you used a Printer Driver to create a PDF output from CADSTAR the document name of the print job was used for the suggested pdf filename (e.g. “Cadstar -
”).
This has been changed so that if a filename has been specified in the Batch Processor then this is used as the document name of the print job. |
| Schematics Design |
Auto Weld Bus |
When you add or move a bus on top of danglers they will be automatically welded together. |
Bus Report |
An active report so selecting the name of a bus in the report highlights the relevant bus on the design. |
Schematic Positional Rename |
Symbols in a Schematic Design can now be renamed according to position. Renaming can be done over multiple sheets and the target range can be specified for each sheet. |
| PCB Design |
| Highlight net |
With one click of the right mouse button you can highlight teardrops and test lands in PCB design. |
| Parts Library Manager fully integrated in Design Editor |
Mirrored View functionality has been added to the P.R.Editor application. It is possible to mirror in the X-Axis or the Y-Axis. All interactive operations are available whilst in the mirrored view. |
| Design Rule Check |
Placement of components will not create a fault message when spacing value is set to "0". |
| Setting – Layers – Documentation
|
Copy your layer stack information (including information on differential pairs) to i.e. Windows Word |
P.R.Editor XR |
| Mirrored View |
Mirrored View functionality has been added to the P.R.Editor application. It is possible to mirror in the X-Axis or the Y-Axis. All interactive operations are available whilst in the mirrored view. |
| Interactive and Automatic Lengthening |
Changes to route patterns of nets that have length constraints set will, during interactive operations be automatically lengthened. |
| Copper as a Target During Auto-routing |
The auto-router has been updated so that it is now possible to consider template copper as a target during auto-routing. This allows tracks of the same signal and same layer as the template copper to connect directly to the poured copper and for tracks of the same signal but on a different layer to connect to the poured copper by way of a via. |
| Outline width for Copper Shapes |
A new option to allow copper shapes to be drawn with an outline width has been added to the Display Properties dialog. |
| P.R.Editor XR HS / SI Verify |
| Impedance Results |
New impedance results are displayed in the CM spreadsheet for differential pairs:
Common mode;
Differential mode;
Even mode and
Odd mode.
These results are displayed in the Impedance tab of the spreadsheet by default. |
| IBIS Termination Models |
IBIS termination models are now supported in the simulation library and for use in SI Verify/PREditor XR HS. |
