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EMC / SI:
CADSTAR SI Verify
According to industry consultants, over 80% of multi-layer PCB
designs are high-speed, needing special design strategies addressing
high-speed effects to ensure successful operation. This trend will
continue in the coming years with the introduction of new low voltage
technologies, increased board density, faster edge rates, and shorter
development cycles. To meet this challenge, the users have to adopt
new methodologies to ensure the designs will work as desired, fulfilling
all signal quality and timing demands. Working to old 'rules of
thumb' will no-longer be adequate to meet these requirements, so
in order to be successful, the users have to adopt new tools that
have simulation capabilities.
CADSTAR SI Verify is a new CADSTAR solution that offers a complete post-layout
signal integrity simulation toolset, seamlessly integrated into CADSTAR. It uses
an accurate transmission line simulation approach to analyze reflection and crosstalk
effects, and to calculate the relevant timing information and delays. It can
be used interactively by the user for selected nets as well as in batch-mode
for an entire PCB sign-off simulation.
The required electrical parameters of transmission lines (phase velocity, inductance
and capacitance matrices, characteristic impedances) are determined by a 2D field
solver using boundary element methods. The time domain signal integrity simulation
offers a fast calculation of reflection and crosstalk effects on printed circuit
boards, considering also the non-linear characteristics of terminations.
Product Information
CADSTAR SI Verify consists of four main components:
- Design Verification Management
- 'What-If' Analysis
- Layer Stack Definition
- Simulation, all sharing the same single Zuken EMC Device Library (EDL).
Design Navigation
The spread-sheet based control cockpit of CADSTAR SI Verify enables hierarchical
design navigation and verification of design constraints against the physical
implementation using interactive or batch simulation.
'What-If' Analysis
A graphical Scenario Editor provides a 'what-if' scratchpad,
allowing the user to experiment with different design strategies. Equivalent
circuits are automatically generated from the physical layout, and various options,
e.g. on terminations or topologies, can be verified through simulation.
Layer Stack Definition
The user can interactively define and modify the layer stack / track cross-sections
to drive the field solver. Determination of the characteristic impedance of
transmission lines, modification of the conductor and dielectric cross-sections,
as well as the used materials is also possible. Cross-sections can be extracted
from the physical design, and own arrangements can be saved as templates. The
user can therefore evaluate the effects of proposed layer stack changes, different
track widths, and track-to-track spacing.
EMC Device Library
The EMC Device Library is used to add and edit behavioral models.
Users can import IBIS standard
device models, and check their behavior and quality graphically, or easily define
their own models. Users can also map to device models in their master library,
or use simple mouse click selection in the design navigation cockpit.
Interactive / Batch Simulation
CADSTAR SI Verify gives the user the option of interactive and batch simulation
in the time or frequency domain. There is no need to define separate models,
and an identical user interface throughout the verification process is provided.
The user can simulate both the physical design and 'What-If' scenarios.
Fast Fourier Transformation
CADSTAR SI Verify's FFT Tab enables the user to view different frequency domain
calculations like voltage, current, and impedance. Coupled Transmission Lines
Interactive reflection and crosstalk simulation results are displayed in a new
simulation control window, with measurement and result export facilities.
Differential pairs
CADSTAR SI Verify simulates differential pairs that are treated as one electrical
entity.
Parameter Sweep
The parameter sweep feature allows the user to experiment with
values of passive devices or lengths of transmission lines in order to determine
the optimal values according to the design requirements. A representation of
all waveforms can be exported to XML or outputs such as CSV, enabling checks
in MS-Excel or other tools.
Eye Diagrams
Waveform visualization can be illustrated in the form of eye diagrams. Allowing you to perform eye-mask verification and to perform analysis based on multi-bit sequence stimuli.
Further
Information
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1.23Mb |
CADSTAR
SI Verify Datasheet |
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1.11Mb |
CADSTAR
Overview Brochure |
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Demonstration
Movie files
A selection of movie files illustrating the CADSTAR
interface in action. |
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