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Routing:
CADSTAR
P.R.Editor XR Rules-by-Area
- Do
you have to compromise your design rules when using BGA’s?
-
Is yield a problem when designing with fine-pitch devices?
CADSTAR
P.R.Editor XR: Rules-by-Area
A
powerful extension to the Zuken P.R.Editor
XR tool-set is the unique Rules-by-Area option that enhances
the best in Zuken’s routing technology by being able to associate
different technology-rules to different areas of the design.
It is
available as a cost-option for the standalone P.R.Editor XR
2000, XR 2000 S, XR
2000 HS, CADSTAR Platinum
Plus, Platinum S Plus
or Platinum HS Plus
and comes as standard with P.R.Editor XR
5000, XR 5000 HS, CADSTAR
Diamond or Diamond
HS.
-
Improve manufacturing yield
-
Reduce layout design times
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Reduce design rule checking violations
-
Automate width/spacing changes
- Automate
via changes
-
Improve routing completion
-
Reduce layer count
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Available with all P.R.Editor XR variants
View
Movie - 1.7Mb
Design
Rule Checking by Areas
In response to the constantly evolving technological and manufacturing
challenges, Zuken has added Rules-by-Area to P.R.Editor XR so that
it can handle designs requiring localized design rules. This cost-option
feature is complemented with full design rule checking in these
areas.
Constraint
Driven
Critical,
dense areas of the design can receive tighter manufacturing related
spacing requirements. This not only improves routing completion,
but ensures that the design will be error free and manufacturable.
Rules-by-Area means more:-
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You can route automatically using reduced track width, via sizes
and spacing around small complex dense components such as BGA’s,
Wire Bonded, CSP’s and SMD to achieve 100% routing and reduce
the layer count.
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All area rules are obeyed dynamically during interactive and automatic
routing.
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No limit to the number of areas defined
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Overlapping areas can be allowed
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Any shape area can be defined
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Areas can be copied and their technology restriction rules will
be maintained
Different
Track Spacings, Widths and Via Sizes for Nominated Areas.
Exceptional
routing detail, e.g. microvias, fine-line tracks and very small
track, via and pad spacings can be specified. This is particularly
appropriate around BGA’S, CSP’s, fine-pitched connectors
and chip-packaging designs.
Improved
Manufacturing Yield
The
relevant nets within the rules area will be routed according to
the exceptional restrictions. This will lead to a significant improvement
in manufacturing yield because only the special area will be subjected
to the fine widths and spacings.
Technology
Rules Supported by Area:
Via
size, Via to Copper, Via to pin, Via to Profile, Via to SMD, Via
to Via, Via to Area, Track width, Track Optional Width, Optional
Track to Pin, Optional Track to Track, Optional Track to Via, Track
to Pin, Track to Via, Track to Track, Track to Copper, Track to
SMD, Track to Area, Track to Profile, Copper to Copper, Copper to
Profile, Pin to Copper, Pin to Pin, Pin to Profile, Pin to SMD,
SMD to Copper, SMD to Profile, SMD to SMD, Testpoint to Testpoint,
Testpoint to Profile.
Further
Information
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