FPGA Synchronisation with Aldec

CADSTAR FPGA combines Aldec's Active-HDL Lite verification tool and Zuken's desktop PCB design suite, CADSTAR, allowing engineers to perform mixed language simulation for vendor neutral FPGAs within the CADSTAR environment.

FPGA data can be imported from Aldec in the CSV file format, which contains pin name, label, swap code, IO bank and position values.

Schematic symbols can be created in CADSTAR by using the schematic symbol block wizard.

The CADSTAR Library Editor can be used to rapidly build the complete part required for SCM & PCB design.

Aldec Active-HDL can be run from CADSTAR, exporting an updated Aldec .csv from CADSTAR en-route, and importing the data back into CADSTAR once Aldec Active-HDL is exited.

For optimum place and route of the PCB Design - pin swapping is required.   Pin swapping in PCB means the characteristic of the pin on FPGA component have also been changed, therefore an updated file in CSV format is to be sent back to FPGA design environment, to update the FPGA implementation.

Similarly changes in the FPGA design environment would require sending an updated CSV format file, to keep the CADSTAR symbols in sync.